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advanced 2-wire serial e 2 prom with block lock tm protection 16k 2048 x 8 bit ? xicor, 1995, 1996 patents pending 6551-2.5 5/13/96 t1/c10/d0 ns 1 characteristics subject to change without notice x24165 functional diagram features ? 2.7v to 5.5v power supply ? low power cmos ? active read current less than 1ma ?active write current less than 3ma ?standby current less than 1 a ? internally organized 2048 x 8 ? new programmable block lock protection ? software write protection ?programmable hardware write protect ? block lock (0, 1/4, 1/2, or all of the e 2 prom array) ? 2 wire serial interface ? bidirectional data transfer protocol ? 32 byte page write mode ? minimizes total write time per byte ? self timed write cycle ? typical write cycle time of 5ms ? high reliability ? endurance: 100,000 cycles ?data retention: 100 years ? available packages ? 8 - lead pdip ?8-lead soic (jedec) ?14-lead tssop description the x24165 is a cmos 16,384 bit serial e 2 prom, internally organized 2048 x 8. the x24165 features a serial interface and software protocol allowing ope ration on a simple two wire bus. three device select inputs (s 0 , s 1 , s 2 ) allow up to eight devices to share a common two wire bus. a write protect regist er at the highest address loca tion, 7ffh, provides three new write protection features: software write protect, block write prote ct, and hardware write protect. the software writ e protect feature prevents any nonvolatile writes to the x24165 until the wel bit in the write protect register is set. the block write protection feature allows the user to individually write protect four blocks of the array by programming two bits in the write protect register. the programmable hardware write protect feature allows the user to install the x24165 with wp tied to v cc , program the entire memory array in place, an d then enable the hardware write protection by programming a wpen bit in the write protect register. afte r this, selected blocks of the array, including the write p rotect register itself, are permanently write protected. xicor e 2 proms are designed and tested for applications requiring extended endurance. inherent data start stop logic control logic slave address register +comparator h.v. generation timing & control word address counter xdec ydec d out ack e 2 prom 64 x 256 data register start cycle v cc r/w pin v ss sda scl s 1 s 0 d out load inc ck 8 6551 ill f01.1 write protect register and logic wp s 2 this x24165 device has been acquired by ic microsystems from xicor, inc. ic mic ic microsystems tm
x24165 2 pin descriptions serial clock (scl) the scl input is used to clock all data into and ou t of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or o pen collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to th e pull- up resistor selection graph at the end of t his data sheet. device select (s 0 , s 1 , s 2 ) the device select inputs (s 0 ,s 1 ,s 2 ) are used to set the first three bits of the 8-bit slave address. this allows up to eight x24165?s to share a common bus. these inputs can be static or actively drive n. if used statically they must be tied to v ss or v cc as appro priate. if actively driven, they must be driven with cmos levels (driven to v cc or v ss ). write protect (wp) the write protect input controls the hardware write protect feature. when held low, hardware write protection is disabled and the x24165 can be writte n normally. when this input is held high, and the wpe n bit in the write protect register is set hi gh, write protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the write protect register itself. pin names 6551 frm t01.2 symbol description s 0 , s 1 , s 2 device select inputs sda serial data scl serial clock wp write protect v ss ground v cc supply voltage nc no connect pin configurations v cc wp scl sda s 0 s 1 s 2 v ss 1 2 3 4 8 7 6 5 x24165 8 - lead dip & soic 6551 ill f02.5 s 0 s 1 nc nc nc s 2 v ss 1 2 3 4 5 6 7 14 13 12 11 10 9 8 v cc wp nc nc nc scl sda x24165 14 - lead tssop
x24165 3 device operation the x24165 supports a bidirectional bus oriented pr o- tocol. the protocol defines any device that sends d ata onto the bus as a transmitter, and the receiving de vice as the receiver. the device controlling the transfer i s a master and the device being controlled is th e slave. the master will always initiate data transfers, and pro vide the clock for both transmit and receive operations. therefore, the x24165 will be considered a slave in all applications. clock and data conventions data states on the sda line can change onl y during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all command are preceded by the start condition, which is a high to low transition of sda when scl is high. the x24165 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. scl sda data stable data change 6551 ill f04 scl sda start bit stop bit 6551 ill f05 figure 1. data validity figure 2. definition of start and stop n otes: (5) typical values are for t a = 25 c and nominal supply voltage (5v) (6) t wr is the minimum cycle time from the system perspect ive when polling techniques are not used. it is the maximum the device requires to perform the internal write o peration.
x24165 4 figure 3. acknowledge response from receiver stop condition all communications must be terminated by a s top condition, which is a low to high transition of sda when scl is high. the stop condition is also used t o place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indica te successful data transfer. the transmitting device , either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock c ycle the receiver will pull the sda line low to ackn owledge that it received the eight bits of data. refer to figure 3. the x24165 will respond with an acknowledge after recognition of a start condition and its slave addr ess. if both the device and a write operation have been s elected, the x24165 will respond with an acknowledge a fter the receipt of each subsequent eight-bit word. in the read mode the x24165 will transmit eight bit s of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected an d no stop condition is generated by the master, the x24165 wi ll continue to transmit data. if an acknowledge is not detected, the x24165 will terminate further data tr ans -missions. the master must then issue a stop condition to retu rn the x24165 to the standby power mode and place the device into a known state. 6551 ill f06 scl from master data output from transmitter 1 8 9 data output from receiver start acknowledge
x24165 5 figure 5. byte write bus activity: master sda line bus activity: x24165 s t a r t slave address s s t o p p a c k a c k a c k word address data 6551 ill f08 device addressing following a start condition the master must output the address of the slave it is accessing (see figure 4) . the next three bits are the device select bits. a system could have up to eight x24165?s on the bus. the eight addresses are defined by the state of the s 0 , s 1 and s 2 inputs. s 1 of the slave address must be the inverse of the s 1 input pin. figure 4. slave address the next three bits of the slave address are an ext ension of the array?s address and are concatenated with the eight bits of address in the word addre ss field, providing direct access to the whole 2048 x 8 array . 6551 ill f07.2 1 a9 a8 r/w device select s 2 s 1 high order word address s 0 a10 device type identifier the last bit of the slave address defines the opera tion to be performed. when set high a read operatio n is selected, when set low a write operation is selecte d. following the start condition, the x24165 mon itors the sda bus comparing the slave address being transmitted with its slave address device type identifier . upon a correct compare the x24165 outputs an acknowledge o n the sda line. depending on the state of the r/ w bit, the x24165 will execute a read or write operation. write operations byte write for a write operation, the x24165 requires a second ad- dress field. this address field is the word address , com- prised of eight bits, providing access to any one o f 2048 words in the array. upon receipt of the word addres s, the x24165 respon ds with an acknowledge and awaits the next eight bits of data, again responding with an a cknowledge the master then terminates the transfer by generati ng a stop condition, at which time the x24165 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the x24165 inputs are disabled, and the device will not respond to an y re quests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence.
x24165 6 figure 6. page write page write the x24165 is capable of a 32 byte page write opera tion. it is initiated in the same manner as the byte wri te operation, but instead of terminating the write cyc le after the first data word is transferred, the mast er can transmit up to fifteen more words. after the receip t of each word, the x24165 will respond with an acknowle dge. after the receipt of each word, the five low order ad- dress bits are internally incremented by one. the high or der bits of the word address remain constant. if the master should transmit more than 32 words prior to generati ng the stop condition, the address counter will ?roll over ? and the previously written data will be over- written. as with the byte write operation, all inputs are disabled u ntil completion of the internal write cycle. refer to fi gure 6 for the address, acknowledge and data transfer sequ ence. acknowledge polling the max write cycle time can be significantly reduc ed using acknowledge polling. to initiate acknowl edge polling, the master issues a start condition follow ed by the slave address byte for a write or read operatio n. if the device is still busy with the high voltage cycl e, then no ack will be returned. if the device has complete d the write operation, an ack will be returned and the host can then proceed with the read or write operat ion. refer to flow 1. flow 1. ack polling sequence 6551 ill f09 write operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed issue stop no yes yes proceed issue stop no bus activity: master sda line bus activity: x24165 s t a r t slave address s s t o p p a c k a c k a c k a c k a c k word address (n) data n data n+1 data n+31 6551 ill f10.1
x24165 7 figure 7. current address read figure 8. random read read operations read operations are initiated in the same manne r as write operations with the exception that the r/w bit of the slave a ddress is set high. there are three basic read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of th e read operation is not a ?don?t care.? to terminate a rea d operation, the master must either issue a stop cond ition during the ninth cycle or hold sda high dur ing the ninth clock cycle and then issue a stop condition. current address read internally the x24165 contains an address counter t hat maintains the address of the last word read, increm ented by one or the exact address of the last word writte n. therefore, if the last access read was to address n , the next read operation would access data from address n + 1. upon receipt of the slave address with the r /w set high, the x24165 issues an acknowledge a nd transmits the eight-bit word. the read operation is terminated by the mast er; by not responding with an acknow -ledge and by issuing a stop condition. refe r to figure 7 for the sequence of address, ack nowledge and data transfer. random read random read operations allow the master to a ccess any memory location in a random manner. prior to issuin g the slave address with the r / w bit set high, the master must first perform a ?dummy? write operation. the master issues the start condition, and the slav e ad- dress with the r/w bit set low, followed by the wor d address it is to read. after the word address ackno wl edge, the master immediately reissues the start condition and the slave address with the r/w bit set high. this will be followed by an acknowledge from the x24165 and then by the eight-bit word. the read oper ation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition . refer to figure 8 for the address, acknowledge and data transfer sequence. bus activity: master sda line bus activity: x24165 s t a r t slave address s s t o p p a c k data 6551 ill f11 bus activity: master sda line bus activity: x24165 s t a r t slave address s a c k 6551 ill f12.1 s t a r t s word address n a c k slave address data n a c k s t o p p
x24165 8 figure 10. typical system configuration sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. the x24165 conti nues to output data for each acknowledge received. the read operation is terminated by the master; by not res ponding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the addr ess counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address spa ce (address 2047), the counter ?rolls over? to 0 and the x24165 continues to o utput data for each acknowledge received. refer to figure 9 for the address, acknowledge and data transfer sequence. bus activity: master sda line bus activity: x24165 slave address a c k 6551 ill f13 a c k data n+x s t o p p data n a c k data n+1 a c k data n+2 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver pull-up resistors sda scl v cc 6551 ill f14 figure 9. sequential read
x24165 9 write protect register the write protect register (wpr) is located at the highest address, 7ffh. figure 11. write protect register wpr.1 = wel ? write enable latch (volatile) 0 = write enable latch reset, writes disabled 1 = write enable latch set, writes enabled if wel = 0 then ?no a ck? after first byte of input data. wpr.2 = rwel ? register write enable latch (volatile) 0 = register write enable latch reset, write s disabled 1 = register write enable latch set, writes enabled wpr.3, wpr.4 = bp0, bp1 ? block protect bits (nonvolatile) (see block protect section for definition) wpr.7 = wpen ? write protect enable bit (nonvolatile) (see hardware write protect section for definition) writing to the write protect register the write protect register is written by performing a random write of one byte directly to address, 7ffh. if a page write is performed starting with any ad dress other than 7ffh, the byte in the array at address 7ffh will be written instead of the write protect register (assuming writes are not disabled by the block prot ect register). the state of the write protect register can be read by performing a random read at address 7ffh at any time. if a sequential read starting at any other ad dress than 7ffh is performed, the contents of the byte in the array at 7ffh is read out instead of the write prot ect register. 7 6 5 4 3 2 1 0 wpen 0 0 bp1 bp0 rwel wel 0 6551 ill f15.1 wpr (addr = 7ffh) wel and rwel are volatile latches that power-up in the low (disabled) state. a write to any address other than 7ffh, where the write protect register is lo cated, will be ignored (no ack) until the wel bit is set high. the wel bit is set by writing 0000001 x to address 7ffh. once set, wel remains high unt il either reset (by writ ing 00000000 to 7ffh) or until the part powers-up again. the rwel bit controls writes to the block protect bits. rwel is set by first settin g wel = 1 and then writing 0000011x to address 7ffh. rwel must be set in order to change the block prote ct b its, bp0 and bp1, or the wpen bit. rwel is reset when the block protect or wpen bits are changed, or when the part powers -up again. programming the bp or wpen bits a three step sequence is required to change the non-volatile block protect or write protect enable: 1) set wel = 1 (write 00000010 to address 7ffh, volatile write cycle) (start) 2) set rwel = 1 (write 00000110 to address 7ffh, volatile write cycle) (start) 3) set bp1, bp0, and/or wpen bits (write w00yz010 t o address 7ffh) w = wpen, y = bp1, z = bp0, (stop) step 3 is a nonvolatile write cycle, requiring 10ms to complete. rwel is reset (0) by this write cycle , requiring another write cycle to set rwel again bef ore the block protect bits can be changed. rwel must be 0 in step 3; if w00yz110 is written to add ress 7ffh, rwel is set but wpen, bp1 and bp0 a re not changed (the device remains at step 2).
x24165 10 block protect bits the block protect bits bp0 and bp1 determine which blocks of the memory are write-protected: programmable hardware write protect the write protect (wp) pin and the write pr otect enable (wpen) bit in the write protect registe r control the programmable hardware write protect fea ture. hardware write protection is enabled when the wp pin and the wpen bit are both hig h, and disabled when either the wp pin is low or the wpen bit is low. when the chip is hardware write-protect ed, non-volatile writes are disabled to the write protect register, including the bp bits and the wpen bit it self, as well as to block -protected sections in the memory array. only the sections of the memory array that a re not block-protected can be written. note that since the wpen bit is write- protected, it cannot be changed back to a low state, and write protection is disabled as long as the the wp pin is held high. t able 2 defines the write protection status for each state of wpen and wp. table 1. block protect bits 6551 frm t02 bp1 bp0 protected addresses 0 0 none 0 1 600h?7ffh upper 1/4 1 0 400h?7ffh upper 1/2 1 1 0000h?7ffh full array (wpr not included) table 2. write protect status table 6551 frm t03 wp wpen memory array (not block protected) memory array (block protected) bp bits wpen bit 0 x writable protected writable writable x 0 writable protected writable writable 1 1 writable protected protected protected
x24165 11 absolute maxim um ratings* temperature under bias x24165 ....................................... ?65 c to +135 c storage temperature ........................ ?65 c to +150 c voltage on any pin with respect to v ss .................................... ?1v to +7v d.c. output current ............................... ............... 5ma lead temperature (soldering, 10 seconds) ...... 300 c * comment stresses above those listed under ?absolute maximum ? ratings? may cause permanent damage to the device. this is a stress rating only and the functional operation o f the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. d.c. operating characteristics 6551 frm t06.1 capacitance t a = +25 c, f = 1mhz, v cc = 5v 6551 frm t07.1 notes: (1)must perform a stop command prior to measurement. (2)v il min. and v ih max. are for reference only and are not 100% tested. (3)this parameter is periodically sampled and not 100% tested. limits symbol parame ter min. max. units test conditions i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100khz, sda = open, all other inputs = v ss or v cc ? 0.3v i cc2 v cc supply current (write) 3 ma i sb1 (1) v cc standby current 50 a scl = sda = v cc , all other inputs = v ss or v cc ? 0.3v, v cc = 5v 10% i sb2 (1) v cc standby current 1 a scl = sda = v cc , all other inputs = v ss or v cc ? 0.3v, v cc = 2.7v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ll (2) input low voltage ?1 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma, v cc = 4.5v symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (s 1 , s 2 , scl) 6 pf v in = 0v recommended operating conditions 6551 frm t04 temperature min. max. commercial 0 c +70 c industrial ?40 c +85 c military ?55 c +125 c 6551 frm t05 supply voltage limits x24165 4.5v to 5.5v x24165-2.7 2.7v to 5.5v
x24165 12 a.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) read & write cycle limits 6551 frm t09.1 power-up timing (4) 6551 frm t10 notes: (4)t pur and t puw are the delays required from the time v cc is stable until the specified operation can be ini tiated. these parameters are periodically sampled and not 100% tested. symbol parameter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 s t buf time the bus must be free before a new transmission can start 4.7 s t hd:sta start condition hold time 4 s t low clock low period 4.7 s t high clock high period 4 s t su:sta start condition setup time (for a repeated start condition) 4.7 s t hd :dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 s t dh data out hold time 300 ns symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms a.c. conditions of test 6551 frm t08.1 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 equivalent a.c. load circuit 6551 ill f16 5v 1533 100pf output
x24165 13 symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance the write cycle time is the time from a va lid stop condition of a write sequence to the end of the int ernal erase/program cycle. during the write cycle, the x24165 bus interface circuits are dis abled, sda is allowed to remain high, and the device does not respond to its slave address. bus timing 6551 ill f17 t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high write cycle limits 6551 frm t11.1 symbol parameter min. typ. (5) max. units t wr (6) write cycle time 5 10 ms bus timing 6551 ill f18 scl sda 8th bit word n ack t wr stop condition start condition notes: (5)typical values are for t a = 25 c and nominal supply voltage (5v). (6)t wr is the minimum cycle time to be allowed from the s ystem perspective unless polling techniques are use d. it is the maximum time the device requires to automatically complete the internal write operation. guideline s for calculating typical values of bus pull-up resistors 6551 ill f19 120 100 80 40 60 20 20 40 60 80100120 0 0 bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k resistance (k )
x24165 14 packaging information 3926 fhd f01 note: 1. all dimensions in inches (in parentheses in mil limeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8 - lead plastic dual in - line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
x24165 15 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ? 8 x 45 3926 fhd f22.1 8 - lead plastic smal l outline gull wing package type s note: all dimensions in inches (in parentheses in m illimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x24165 16 note: all dimensions in inches (in parentheses in m illimeters) 14 - l ead plastic, tssop package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 ? 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) 3926 fhd f32 packaging information
x24165 17 ordering information part mark convention device x24165 p t g - v temperature range blank = 0 c to +70 c i = ?40 c to +85 c m = ?55 c to +125 c package p = 8-lead plastic dip s = 8-lead soic (jedec) v = 14 -lead tssop p = 8-lead plastic dip blank = 8-lead soic (jedec) v = 14 -lead tssop g = rohs compliant lead free blank = 4.5v to 5.5v, 0 c to +70 c i = 4.5v to 5.5v, ?40 c to +85 c f = 2.7v to 5.5v, 0 c to +70 c g = 2.7v to 5.5v, ?40 c to +85 c x24165 x g x limited warranty devices sold by xicor, inc. are covered by the warr anty and patent indemnification provisions appearin g in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by descri ption regarding the information set forth herein or regarding the freedom of the described devices fro m patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xico r, inc. reserves the right to discontinue productio n and change specifications and prices at any time an d without notice. xicor, inc. assumes no responsibility for the use o f any circuitry other than circuitry embodied in a xicor, inc. product. n o other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the follo wing u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,5 33,846; 4,599,706; 4,617,652; 4,668,932; 4,752, 912; 4,829, 482; 4,874, 967; 4,883, 976. foreig n patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this pro duct should design the system with appropriate error detection and correction, redunda ncy and back-up features to prevent such an occuren ce. xicor's products are not authorized for use in crit ical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical impla nt into the body, or (b) support or sustain life, and whose fa ilure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.a critical component is any component of a life s upport device or system whos e failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. v cc range blank = 4.5v to 5.5v 2.7 = 2.7v to 5.5v g= rohs compliant lead free package blank = standard package. non lead free

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